Samsung Electronics is aggressively promoting the performance and energy efficiency gains of its most advanced memory hardware, aiming to outpace competitors SK Hynix and Micron Technology.

On August 4, at the FMS annual storage industry summit, Samsung Electronics officially announced two conceptual products, zHBM and zNAND-O, as well as the industry's first V10 BV-NAND, which uses wafer bonding technology and stacks over 400 layers.

Among these, zHBM directly vertically stacks high-bandwidth memory on top of AI accelerator chips, with performance expected to be approximately eight times that of the next-generation HBM5.

These technology announcements come at a time of intense competition in the memory industry. As noted by Wall Street News, SK Hynix, in collaboration with SanDisk, jointly released the first global standard specification for High Bandwidth Flash (HBF) at the conference.

HBF technology is positioned as a new storage tier between High Bandwidth Memory (HBM) and Solid-State Drives (SSD), aiming to address both bandwidth bottlenecks and capacity expansion challenges in AI inference scenarios.

zHBM Disrupts Traditional Packaging Architecture

zHBM is the most anticipated technology vision from this announcement. In current designs, an HBM memory stack and an AI chip are integrated side-by-side within the same package using a silicon interposer, a configuration commonly referred to as 2.5D packaging. Companies like AMD and Nvidia use this approach for high-end AI applications.

Samsung's zHBM breaks this paradigm by directly stacking HBM vertically on top of the AI accelerator chip. Samsung states that by significantly shortening the data transmission distance between the AI processor and memory, zHBM can deliver higher bandwidth and superior energy efficiency, meeting the ultra-fast data processing demands of large-scale AI training and inference.

According to specifications released by Samsung, combined with next-generation wafer bonding technology, zHBM can achieve a memory density over ten times that of HBM5, a threefold improvement in energy efficiency, and a more than 50% reduction in thermal resistance. The technology also supports customized IP integration, allowing for the embedding of custom designs in the intermediate layer between the memory and the AI accelerator, further expanding memory capacity and enhancing accelerator performance.

Samsung has set a tentative mass production timeline for this technology around 2029, but has not yet provided a clear schedule for either HBM5 or zHBM. Meanwhile, Samsung stated that it has already started mass production of HBM4 based on 1c DRAM process technology and a 4nm base die since February, and shipped initial HBM4E samples to global customers in May.

Targeting HBF: A High-Bandwidth Flash Solution for Edge AI

Samsung also introduced zNAND-O, its next-generation high-performance NAND solution built on V-NAND technology. The target mass production date is 2028, and it will be available in four-layer and eight-layer versions. Technologically, zNAND-O is similar to the High Bandwidth Flash (HBF) concept previously developed by SK Hynix and SanDisk, also utilizing TSV and UCIe interfaces.

However, according to Samsung officials, there is a fundamental difference in the application positioning of the two: HBF is designed to fill the memory hierarchy gap next to AI accelerators on the server side, whereas zNAND-O is positioned to store large models in edge devices for interaction with NPUs. Samsung states that zNAND-O, with its high spatial efficiency, improved I/O performance, and low latency, is specifically optimized for edge AI environments supporting real-time, data-intensive AI applications.

V10 BV-NAND: Industry's First 400+ Layer Wafer-Bonded Flash

Samsung also unveiled the V10 BV-NAND, its first 3D NAND product to use a Bonding V-NAND architecture. This milestone update arrives 13 years after Samsung introduced the industry's first V-NAND technology at the Flash Memory Summit in 2013. The V10 BV-NAND stacks over 400 layers, vertically stacking memory cells using wafer bonding technology, resulting in a storage density approximately 58% higher than the previous generation V9. Additionally, the product offers improvements in read, write, and I/O performance compared to its predecessor, aiming to provide high-performance, high-capacity NAND support for future AI systems and applications.

Comprehensive AI Memory Portfolio: From HBM to PIM and Enterprise Storage

Beyond these cutting-edge concept products, Samsung systematically showcased its existing AI memory and storage product portfolio and roadmap at the exhibition, covering product lines such as HBM4E, HBM5, LPDDR5X-PIM, and PM1763. Among these, LPDDR5X-PIM is the industry's first LPDDR memory featuring Processing-in-Memory technology, allowing data processing to be performed directly within the memory, which can improve both data transfer efficiency and power consumption. In the enterprise storage segment, Samsung showcased the PM1763 and BM1773 solutions, tailored to meet the growing storage demands of AI data centers. As the only integrated device manufacturer (IDM) with industry-leading capabilities in memory, foundry, and advanced packaging, Samsung positions these products as one-stop, end-to-end AI infrastructure solutions, aiming to help customers shorten development cycles and accelerate the market introduction of differentiated AI semiconductor products.