Samsung Electronics has formally disclosed the core technology roadmap for its next-generation High Bandwidth Memory HBM5, confirming the adoption of a 2-nanometer process featuring GAA architecture in the base die. The goal is to increase speed by more than 50% over the HBM4E while significantly enhancing power efficiency.

This information originates from an interview published on July 27 by Samsung Semiconductor's official newsroom, featuring Jaesun Koo, Vice President and Head of the Technology Development Office for the Foundry Business at Samsung Electronics' Device Solutions Division. This represents Samsung's clearest articulation to date of HBM5's technical specifications and process roadmap, signaling a new phase in the deep integration of memory and logic processes within the AI chip arms race. For investors closely monitoring whether Samsung can regain a competitive edge in the HBM market, this disclosure provides a crucial signal of technological progress.

Samsung also revealed that its foundry division initiated mass production of the first-generation 2nm process in the second half of last year. It plans to commence mass production of a second-generation 2nm process, which boasts further improvements in performance and yield, in the second half of this year for new mobile applications. Additionally, Samsung disclosed that it has secured orders for automotive-grade 2nm products from Tesla and continues to receive follow-up orders from several major AI, HPC, and cloud service provider customers.

HBM5 Base Die Targets 2nm GAA, Speed Goal Soars 50%

According to Samsung's official disclosure, the base die for HBM5 will utilize a 2nm process with GAA (Gate-All-Around) transistor architecture and will achieve higher-density TSV (Through Silicon Via) interconnects. Koo stated that HBM5 is expected to require a speed improvement of approximately 50% or more over HBM4E. Consequently, the base die must incorporate the most advanced process capable of delivering substantial leaps in both speed and power efficiency.

In the HBM stack structure, the base die sits beneath the Core Die, functioning as a high-speed data interface between external processors like GPUs and CPUs and the HBM memory. Starting from the HBM4 generation, Samsung began introducing advanced foundry processes into the base die, replacing previously used memory processes to enhance overall performance and energy efficiency. The base dies for HBM4 and HBM4E utilize Samsung's fourth-generation 4nm foundry process, supporting high-speed operation above 14Gbps and reducing power consumption and improving heat dissipation paths through optimized metal wiring layers.

Vertical Integration Advantage: Design, Manufacturing, and Packaging Under One Roof

Samsung positions its HBM products as "Turn-key" solutions—the Core Die is manufactured by the memory division, the base die is produced by the foundry division, and the final packaging is completed by the TSP (Advanced Packaging) division. The entire process is handled internally at Samsung.

Koo pointed out that this vertically integrated architecture enables Samsung to have the memory, foundry, and packaging divisions collaborate from the design stage to optimize speed, power consumption, heat dissipation, and yield. This collaboration shortens the mass production cycle and reduces costs. Using the HBM4 base die development as an example, he noted that performance and yield targets were met simultaneously starting from the first samples, with the entire process taking only about three months. Samsung internally recognizes this as its "best success case."

Foundry Business Diversification: Extending from Mobile to AI, Automotive, and Robotics

While disclosing the HBM5 roadmap, Samsung's foundry division also elaborated on its expansion strategy into non-mobile markets. Koo stated that Samsung Foundry has proven its process competitiveness by securing orders for automotive-grade 2nm products from Tesla and has leveraged this momentum to continuously win orders from major AI, HPC, and cloud service provider customers.

In the AI/HPC field, Samsung offers a one-stop solution encompassing advanced packaging and high-bandwidth memory. In the data center domain, Samsung has entered the PO (Pluggable Optics) business and is developing foundational technology for CPO (Co-Packaged Optics) based on advanced processes and 3D packaging technology. In the automotive and robotics sectors, Samsung is also expanding technical cooperation with clients and strengthening the competitiveness of special processes such as eMRAM, millimeter-wave, and RF.

Koo stated that Samsung Foundry will leverage the experience and technical competitiveness gained from the 4nm HBM4 base die to be the first to introduce the 2nm process for HBM5, aiming to "solidify its technological leadership."